1. Field of the Invention
The present invention relates to a semiconductor device including a semiconductor evaluation element for evaluating characteristics, and an evaluation method using the semiconductor device.
2. Description of the Related Art
The inventor(s) of the present invention conducted the following analyses.
Characteristics of insulated gate field effect transistors are measured using an evaluation circuit and an evaluation element which are called as a test element group (TEG). For example, an insulated gate field effect transistor such as a metal oxide semiconductor field effect transistor (MOSFET) has a contact resistance between an electrode layer such as a source or a gate and a diffusion layer in a semiconductor. The contact resistance affects a direct current (DC) characteristic such as a transconductance (gm) and a high-frequency characteristic such as a cutoff frequency.
For example, JP 09-064139 A discloses an evaluation element and an evaluation circuit which evaluate characteristics of the insulated gate field effect transistor with and without the influence of the contact resistance. The evaluation element includes a first diffusion layer region and a second diffusion layer region between which a gate electrode of the insulated gate field effect transistor to be evaluated is interposed. A drain electrode is connected with the first diffusion layer and a source electrode is connected with the second diffusion layer. A first electrode connected with the first diffusion layer is formed father from the gate electrode than the drain electrode on the first diffusion layer. A second electrode connected with the second diffusion layer is formed father from the gate electrode than the source electrode on the second diffusion layer. A first measurement terminal is connected with the gate electrode through a first wiring. A second measurement terminal and a third measurement terminal are connected with the drain electrode through a second wiring. A fourth measurement terminal is connected with the first electrode through a third wiring. A fifth measurement terminal and a sixth measurement terminal are connected with the source electrode through a fourth wiring. A seventh measurement terminal is connected with the second electrode through a fifth wiring. The evaluation circuit, using all of the measurement terminals in the evaluation element, enables to evaluate the characteristics of the insulated gate field effect transistor with and without the influence of the contact resistance.
Recently, it has been reported that current characteristics of a MOS transistor are significantly affected depending on the number of contacts and a contact position in the MOS transistor in the case where an element size reduces (for example, “Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90 nm SOI ULSI Technology” R. Q. Williams, D. Chidambarrao, J. H. McCullen, S. Narasimha, T. G. Mitchell and D. Onsongo, NTSI-Nanotech 2006, www.nsti.org, ISBN 0-9767985-8-1 Vol. 3, 2006). This indicates that a stress applied to the channel region by a stopper film is reduced by the formed contacts to significantly affect the current characteristics.
Developed advanced processes include a technique using such an effect to form a CAP film (stopper film) for applying the intended stress to the channel region in order to improve the characteristics of the MOS transistor. However, the stress applied by the CAP film varies according to a contact formation condition to significantly affect the DC characteristic of the MOS transistor. Therefore, it is important to analytically estimate the amount of DC variation of the MOS transistor which is caused by the formed contacts.
Characteristics of semiconductor elements are measured using an evaluation circuit including an evaluation element called as the test element group (TEG). The following analyses are given by the present invention. For example, as shown in FIG. 1A, an evaluation element for measuring a direct current (DC) characteristic of a metal oxide semiconductor field effect transistor (MOSFET) includes diffusion layers 102 and 103 which are provided on both sides of a gate 101 and correspond to a source and a drain. Metal layers 108 and 109 serving as wirings are connected with the diffusion layers 102 and 103 through contacts 105 and 106. Voltages are applied to respective portions of the MOS transistor and currents flowing at this time are observed to measure the DC characteristic.
When DC characteristic is to be measured, as shown in FIGS. 1A and 1B, a plurality of evaluation elements whose distances CR between the gate 101 and the contact 105 (106) are different from each other are prepared and a current value is measured for each of the evaluation elements. Therefore, a diffusion layer resistance can be estimated with the distance CR as a parameter, based on the changes in the current value for each of the evaluation elements.
However, even when the influence of a variation in stress which is caused according to the contact position is to be determined using the DC measurement layout of the MOS transistor which is disclosed in JP 09-064139 A or the DC measurement layout shown in FIGS. 1A and 1B, not only a variation in DC characteristic due to the variation in stress but also a variation in parasitic resistance component of the diffusion layer resistance occurs. As a result, the DC change caused by the stress cannot be separated from the DC change caused by parasitic resistance.